The present invention relates to a process for displaying data on a matrix display, more particularly a matrix display consisting of N data lines and M selection lines at the intersections of which are situated image points or pixels, and in which the N data lines are grouped into P blocks of N′ data lines each.
Among matrix displays, the liquid crystal screens used in direct viewing mode or in projection mode are in particular known. These screens are, in general, composed of a first substrate comprising selection lines, hereinafter referenced lines, and data lines, hereinafter referenced columns, at the intersections of which are situated the image points and of a second substrate comprising a back electrode, the liquid crystals being inserted between the two substrates. The image points consist in particular of pixel electrodes connected across switching circuits, such as transistors, to the selection lines and the data lines. The selection lines and the data lines are respectively connected to peripheral control circuits generally referred to as “drivers”. The line drivers scan the lines one after another and close the switching circuits, that is to say turn on the transistors of each line. On the other hand, the column drivers apply a cue to each data line, that is to say they charge the electrodes of the selected pixels and modify the optical properties of the liquid crystal contained between these electrodes and the back electrode, thus allowing the formation of images on the screen. When the matrix display comprises a limited number of lines and columns, each column is connected by its own connection line to the column drivers of the screen.
In the case of a screen with high definition, the principle of multiplexing is used between the outputs of the column driver and the columns of the screen in such a way as to reduce the number of tracks at the input of the cell. Thus, in French patent application No. 96 00259 filed on 11 Jan. 1996 in the name of the Applicant, there is described a column control circuit of a matrix display such as represented in FIG. 1. In this case, the columns are grouped into P blocks 1 of N′ columns, i.e. 9 columns C1, C2, C3 . . . C9 in the embodiment represented. Each block consists of transistors 3, one of the electrodes of which is linked to a column and the other electrode of which is connected to the same electrode of the other transistors of the block, together these electrodes being connected to a video input referenced DB1 for the first block, DB2 for the second block, DBP for the last block. The gates of the transistors 3 each receive a demultiplexing signal DW1, DW2, DW3 . . . DW9. Each block exhibits the same structure.
The timing diagrams for the voltages read off from the successive columns of one and the same block 1 receiving a video signal DB1 to DBP are represented in FIG. 2. In plotting these timing diagrams it has been assumed that the DC and AC voltage errors introduced by column-line-column coupling (referenced 2 in FIG. 1), the origin of which was described in French patent No. 96 00259 filed on 11 Jan. 1996, are perfectly corrected by the compensation circuit presented in this same patent. Each timing diagram represents a line time of a given column (1 to 9) of a block connected for example to DB1. In the case of a line time of 32 μs, the signals can be broken down as follows:
1.Precharging of all the columns of the4μsmatrix2.Stabilization of the precharge0.5μs3.Sampling of the video over the 9 columns9 × 2μsof the block DB4.Equalization between column and pixel7.5μs
These diagrams show that the voltage of the columns and hence the RMS voltage across the terminals of the liquid crystal cell, the electrodes of which are respectively the column and the electrode CE opposite, changes according to the order of sampling of the columns of a block connected to DBP. Now, since the dielectric constant of the liquid crystal varies as a function of the voltage applied to its terminals, the columns of one and the same block receiving a signal DBi do not therefore exhibit the same charging capacity. Consequently, the coupling between the gates of the sampling transistors and the columns of one and the same block receiving the signal DBi increases as a function of the order of sampling of the columns, this introducing a DC error of several tens of mV between the first column sampled in the block receiving the signal DBi and the last.
The purpose of the present invention is to propose a process for displaying data on a matrix display which makes it possible to remedy this drawback.